1. Field of the Invention
The present invention relates generally to a semiconductor memory device and, more particularly, to a flash memory device and a voltage generating circuit for the same.
2. Description of the Related Art
Semiconductor memories are usually considered to be the most vital microelectronic component of digital logic system design. Semiconductor memories may be used in various fields such as, for example, computers, microprocessor-based applications ranging from satellites to consumer electronics, etc. Because of the large usage of semiconductor memories in various fields, there is a need and value associated with innovations in the field of semiconductor memory fabrication. Some of these innovations may include enhancements in the semiconductor fabrication process and technology that may lead to an increase in the density and processing speed of semiconductor memories.
Generally, semiconductor memory devices may be classified into volatile memory devices and non-volatile memory devices. The volatile memory devices may be classified into dynamic random access memories (DRAMs) and static random access memories (SRAMs). Volatile memory devices may suffer from some limitations. For example, volatile memory devices may lose their data when their power supplies are interrupted. On the other hand, non-volatile memory devices may retain their stored data even when their power supplies are interrupted. Therefore, non-volatile memories may be widely used to store data that has to be retained irrespective of power supply interruption. Non-volatile memory may include, for example, mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs).
Flash memory devices may be categorized as NOR-type and NAND-type flash memory. This categorization is based on the arrangement of memory cells. Specifically, in a NOR-type flash memory device, at least two cell transistors are connected in parallel to a bitline and data may be stored by means of a channel hot electron and erased by means of Fowler-Nordheim tunneling (F-N tunneling).
On the other hand, a NAND-type flash memory device may include at least two cell transistors connected in series to a bitline. Furthermore, the data is stored and erased by means of F-N tunneling. NOR-type flash memory devices may have certain limitations. For example, an increase in their integration density may cause an increase in power consumption. However, a NOR-type flash memory may perform well at high operating speeds. In recent years, multi-level cell (hereinafter referred to as “MLC”) technologies have been used to increase the integration density of NOR-type flash memory devices.
FIG. 1 illustrates threshold voltages of a flash memory cell and the distributions of corresponding data. Specifically, FIG. 1 illustrates threshold voltage distributions of an MLC in which 2-bit data is stored and where the data values correspond to respective threshold voltages.
For example, when single-bit data is stored in a flash memory, data stored in a unit cell may be expressed as two threshold voltage distributions each, corresponding to data ‘1’ and data ‘2’. Alternatively, when multi-bit data is stored in a flash memory device, data stored in a unit cell may be expressed by four threshold voltage distributions each corresponding to data ‘11’, data ‘10’, data ‘00’, and data ‘01’, as illustrated in FIG. 1. Values of data stored in a cell may be arranged as follows: ‘11’, ‘10’, ‘00,’ and ‘01’. In this case, the values may be arranged according to the descending order of states of a cell threshold voltage. In general, the state ‘11’ is an erased state and a program operation starts from the state ‘11’.
A plurality of constant voltages are required for programming, erasing, and reading single-bit/multi-bit data to/from a flash memory cell. The constant voltages are generated from a voltage generating circuit. Among the constant voltages, program verify voltages Vvrf0, Vvrf1, Vvrf2, and Vvrf3, and read voltages Vread1, Vread2, and Vread3 are shown in FIG. 1. The voltages shown in FIG. 1 are merely part of a set of constant voltages generated from a voltage generating circuit. As is well known in the art, with an increase in the bit number of data stored in each cell, more levels of a wordline voltage may be required for programming, erasing, and reading the stored data.
Generally, each constant voltage may be generated through an independent charge pump and an independent regulating circuit. However, using a separate charge pump to generate separate voltage levels may pose some problems. For example, an additional control signal may be required for generating and maintaining each constant voltage. Furthermore, an additional circuit may also be required for controlling the additional control signal. Therefore, as levels of a wordline voltage increase in number, the configuration of a circuit required for generating each voltage may become complex and the chip size may have to be increased to accommodate the increase in the number of circuits. Moreover, the characteristics of each regulating circuit may vary because of the difference in the process of designing and fabricating each circuit. This difference in fabrication and/or design processes may lead to an increase in the difference between the voltages generated by each regulating circuit. Therefore, a sensing margin used to determine the data stored in the cells may be reduced.